Compiler method for generating instructions for vector operations in a multi-endian instruction set
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 1, 2019
Grant Date -
Jun 23, 2016
app pub date -
Dec 19, 2014
filing date -
Dec 19, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a bi-endian environment, wherein the processor architecture contains instructions with an inherent endian bias, along with at least one memory access instruction with a contrary endian bias. The compiler uses a code generation endian preference that matches the inherent computer system endian bias. The compiler generates instructions for vector instructions by determining whether the vector instruction has an endian bias that matches the code generation endian preference. When the endian bias of the vector instruction matches the code generation endian preference, the compiler generates one or more instructions for the vector instruction as normal. When the endian bias of the vector instruction does not match the code generation endian preference, the compiler generates instructions that include one or more vector element reverse instructions to fix the mismatch.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully