Instruction and logic for tracking access to monitored regions
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United States of America Patent
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Apr 18, 2017
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app pub date -
Dec 23, 2014
filing date -
Dec 23, 2014
priority date (Note) -
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Abstract
A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a tracking instruction to enable tracking of execution of a region of memory. The instruction is to define an address range of the region. The retirement includes logic to retire the tracking instruction and candidate instructions. The performance monitoring unit includes logic to determine that the candidate instructions are associated with an entrance and an exit to the address range, and to generate an alert based on the candidate instructions association with the entrance and the exit.
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