Partial spacer for increasing self aligned contact process margins

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United States of America Patent

PATENT NO 9496368
SERIAL NO

14576436

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Abstract

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A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate. The semiconductor includes a first set of sidewall spacers on opposite sidewalls of the gate stack. The semiconductor includes a flowable dielectric layer on the substrate, covering at least a portion of the first set of sidewall spacers. The semiconductor includes a second set of sidewall spacers next to the first set of sidewall spacers covering an upper portion thereof, the second set of sidewall spacers are directly on top of the flowable dielectric layer. The semiconductor includes a contact next to at least one of the second set of sidewall spacers.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Alptekin, Emre Fishkill, US 91 966
Ramachandran, Ravikumar Pleasantville, US 128 2157
Sardesai, Viraj Y Poughkeepsie, US 45 567
Vega, Reinaldo A Wappingers Falls, US 91 1196

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