CMOS Schmitt trigger circuit and associated methods
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United States of America Patent
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Oct 11, 2016
Grant Date -
Jun 23, 2016
app pub date -
Dec 17, 2014
filing date -
Dec 17, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
The Schmitt trigger circuit includes a signal input, a first inverter coupled to the signal input and configured to operate at a first voltage, and a second inverter coupled downstream of the first inverter and configured to operate at a second voltage lower than the first voltage. A protection device is coupled between the first inverter and the second inverter, and configured to limit a voltage input to the second inverter at the second voltage. A feedback circuit is coupled downstream of the protection device between the first inverter and the second inverter and configured to introduce hysteresis. An output circuit is coupled to the second inverter and configured to provide an output signal at the second voltage. The approach provides an architecture for 3.3V receivers designed by using 1.8V devices, without active power consumption from the I/O PAD during transition, and/or that supports CMOS standard levels for 1.8V and 3.3V receivers.
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