Information processing device including nonvolatile cache memory and processor
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United States of America Patent
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Nov 12, 2019
Grant Date -
Jun 30, 2016
app pub date -
Mar 12, 2015
filing date -
Dec 29, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
According to one embodiment, a cache memory device includes a nonvolatile cache memory, write unit, determination unit, selection unit, and erase unit. The nonvolatile cache memory includes a plurality of erase unit areas. Each of the erase unit areas includes a plurality of write unit areas. The write unit writes data to the nonvolatile cache memory. The determination unit determines whether the plurality of erase unit areas satisfy an erase condition or not. The selection unit selects an area to be erased from the plurality of erase unit areas when the plurality of erase unit areas satisfy the erase condition. The erase unit erases the data written to the area to be erased.
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