Memory control circuit and cache memory
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 10, 2017
Issued Date -
N/A
app pub date -
Mar 3, 2016
filing date -
Sep 6, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory control circuit to control a first memory comprising a plurality of MRAM cells, each MRAM cell including of a magnetoresistive element to store data, has a second memory, when there is a read request to a first address of the first memory, to read data of a second address different from the first address, from the first memory and store the read data, a controller to control access to the first memory and the second memory, a capacitor connected in series to the magnetoresistive element, and a sense amplifier to sense a logic of the data from a voltage between both electrodes of the capacitor, the voltage varying in accordance with a current flowing through the magnetoresistive element.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully