Method and Apparatus for Predictive and Adaptive Power Management of Memory Subsystem Based on memory access Information
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United States of America Patent
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Issued Date -
Jul 24, 2014
app pub date -
Jan 23, 2013
filing date -
Jun 5, 2002
priority date (Note) -
Abandoned
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Abstract
A method and apparatus are disclosed for performing adaptive memory power management in a system employing a CPU and a memory subsystem. A CPU throttle control (THR) module generates a CPU throttle control signal indicating when the CPU is idle. A memory controller (MC) module generates memory power management signals based on at least one of the CPU throttle control signal, memory read/write signals, memory access break events, and bus master access requests. Certain portions of the memory subsystem are powered down in response to the memory power management signals. Memory power management is performed on a time segment by time segment basis to achieve efficient power management of the memory subsystem during CPU run time.
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