Cache operations for memory management

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9645938
APP PUB NO 20160203085A1
SERIAL NO

14127483

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Abstract

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In accordance with the present description, cache operations for a memory-sided cache in front of a backing memory such as a byte-addressable non-volatile memory, include combining at least two of a first operation, a second operation and a third operation, wherein the first operation includes evicting victim cache entries from the cache memory in accordance with a replacement policy which is biased to evict cache entries having clean cache lines over evicting cache entries having dirty cache lines. The second operation includes evicting victim cache entries from the primary cache memory to a victim cache memory of the cache memory, and the third operation includes translating memory location addresses to shuffle and spread the memory location addresses within an address range of the backing memory. It is believed that various combinations of these operations may provide improved operation of a memory. Other aspects are described herein.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gries, Matthias Braunschweig, DE 10 266
Kranich, Tim Braunschweig, DE 5 87
Linkewitsch, Niklas Evessen, DE 17 127

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