MEMORY DEVICE, RELATED METHOD, AND RELATED ELECTRONIC DEVICE
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United States of America Patent
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Issued Date -
Jul 14, 2016
app pub date -
Dec 31, 2015
filing date -
Dec 31, 2015
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A memory device may include a first p-channel transistor, a first n-channel transistor, a first inverter, and a first access transistor. A source terminal of the first p-channel transistor is electrically connected to a first power supply terminal. A source terminal of the first n-channel transistor is electrically connected to a second power supply terminal. A first source terminal of the first inverter is electrically connected, without through any intervening transistor, to a drain terminal of the first p-channel transistor. A second source terminal of the first inverter is electrically connected to a drain terminal of the first n-channel transistor. A drain terminal of the first access transistor is electrically connected to an output terminal of the first inverter. A gate terminal of the first access transistor is electrically connected to a gate terminal of the first p-channel transistor.
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