Integrating VLSI-compatible fin structures with selective epitaxial growth and fabricating devices thereon

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United States of America Patent

PATENT NO 9685381
SERIAL NO

14777736

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Abstract

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Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chau, Robert S Beaverton, US 514 18980
Chu-Kung, Benjamin Portland, US 216 2234
Dewey, Gilbert Hillsboro, US 439 4094
Goel, Niti Portland, US 38 513
Kavalieros, Jack T Portland, US 510 7874
Metz, Matthew V Portland, US 331 5764
Mukherjee, Niloy Portland, US 230 3769
Pillarisetty, Ravi Portland, US 449 7344
Rachmady, Willy Beaverton, US 425 5611
Radosavljevic, Marko Beaverton, US 465 4706

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