CHIP PACKAGE AND FABRICATION METHOD THEREOF
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United States of America Patent
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Issued Date -
Jul 14, 2016
app pub date -
Jan 11, 2016
filing date -
Jan 12, 2015
priority date (Note) -
Published
status (Latency Note)
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Abstract
A chip package including a chip, a first though hole, a conductive structure, a first isolation layer, a second though hole and a first conductive layer. The first though hole is extended from a second surface to a first surface to expose a conductive pad, and the conductive structure is on the second surface and extended to the first though hole to contact the conductive pad. The conductive structure includes a second conductive layer and a laser stopper. The first isolation layer is on the second surface and covering the conductive structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stopper, and the first conductive layer is on the third surface and extended to the second though hole to contact the laser stopper.
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