Methods of forming dislocation enhanced strain in NMOS structures

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United States of America Patent

PATENT NO 10396201
APP PUB NO 20160204256A1
SERIAL NO

14912594

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Abstract

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Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

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Patent Owner(s)

  • INTEL CORP.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Glass, Glenn Beaverton, US 30 102
Jackson, Michael Portland, US 145 3499
Mohapatra, Chandra Beaverton, US 9 16
Morarka, Saurabh Hillsboro, US 16 19
Murthy, Anand Portland, US 186 3970

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