Cladding layer epitaxy via template engineering for heterogeneous integration on silicon

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 10693008
APP PUB NO 20160204263A1
SERIAL NO

14914906

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Abstract

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An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.

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Patent Owner(s)

  • INTEL CORP.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chu-Kung, Benjamin Hillsboro, US 216 2234
Dewey, Gilbert Hillsboro, US 438 4094
Goel, Niti Portland, US 38 513
Kavalieros, Jack T Portland, US 510 7874
Le, Van H Portland, US 269 2810
Mukherjee, Niloy Portland, US 230 3769
Pillarisetty, Ravi Portland, US 449 7344
Radosavljevic, Marko Portland, US 465 4706

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