Test structure to measure delay variability mismatch of digital logic paths
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United States of America Patent
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Nov 28, 2017
Grant Date -
Jul 21, 2016
app pub date -
Jan 20, 2016
filing date -
Jan 21, 2015
priority date (Note) -
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Abstract
An integrated circuit includes a test block which in turn includes a plurality of identical paths; a counter selectively coupled to the plurality of identical paths to selectively obtain a count of at least one of correctly operating paths and incorrectly operating paths from each of the plurality of identical paths; and a plurality of count latches selectively coupled to the counter to store output of the counter. Each path in turn includes a first clocked latch; a clocked logic path beginning and ending at the first clocked latch; and a clocked detection circuit coupled to the first clocked latch and the counter, which determines whether the clocked logic path is operating properly in a given clock period.
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