LAMINATED CHIP AND LAMINATED CHIP MANUFACTURING METHOD
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United States of America Patent
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Issued Date -
Jul 21, 2016
app pub date -
Dec 15, 2015
filing date -
Jan 19, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A laminated chip includes: a first chip; a first wiring layer formed on the first chip; a second chip; a second wiring layer formed on the second chip; and a layer disposed between the first wiring layer and the second wiring layer, the layer includes an adhesive agent configured to bond the first wiring layer and the second wiring layer; a plurality of first bumps connected to the first wiring layer; a plurality of second bumps connected to the second wiring layer; and solder connected to the plurality of first bumps and the plurality of second bumps.
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