Low-power retention flip-flops
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United States of America Patent
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Apr 17, 2018
Issued Date -
N/A
app pub date -
Oct 26, 2015
filing date -
Jan 15, 2015
priority date (Note) -
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Abstract
A retention flip-flop is provided. The flip-flop includes a clock generation circuit, a master latch circuit, and a salve latch circuit. The clock generation circuit generates first and second clock signals in a first mode. The master latch circuit performs a first latch operation on an input signal from the input terminal according to the first and second clock signals to generate a first latched signal at a first node in the first mode. The salve latch circuit performs a second latch operation on the first latched signal according to the first and second clock signals to generate a second latched signal at a second node in the first mode. In a sleep or power-down mode, the total number of transistors in the clock generation circuit and the salve latch circuit is equal to or less than eight.
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