Apparatus and method for controlling level 0 cache
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United States of America Patent
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Nov 21, 2017
Issued Date -
N/A
app pub date -
Jan 26, 2016
filing date -
Feb 3, 2015
priority date (Note) -
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Abstract
Disclosed herein is an apparatus and method for controlling level 0 caches, capable of delivering data to a processor without errors and storing error-free data in the caches even when soft errors occur in the processor and caches. The apparatus includes: a level 0 cache #0 connected to the load/store unit of a first processor; a level 0 cache #1 connected to the load/store unit of a second processor; and a fault detection and recovery unit for reading from and writing to tag memory, data memory, and valid bit memory of the level 0 cache #0 and the level 0 cache #1, performing the write-back and flush of the level 0 cache #0 and the level 0 cache #1 based on information stored therein, and instructing the load/store units of the first and second processors to stall a pipeline and to restart an instruction #n.
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