METHOD AND APPARATUS FOR LOGICAL DESIGN CONNECTIVITY-BASED AUTOMATIC MACRO PLACEMENT
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United States of America Patent
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Issued Date -
Aug 11, 2016
app pub date -
Feb 11, 2015
filing date -
Feb 11, 2015
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Abandoned
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Abstract
A method, system, and computer-readable medium are described that enable efficient design processes for integrated circuits. In particular, tools are described which enable an integrated circuit designer to visualize an integrated circuit design without combinational logic and, from such visualization, identify locations in the design of common node logical connectivity. This information enables the designer to identify potential areas where the integrated circuit design can be improved.
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