Bumpless die-package interface for bumpless build-up layer (BBUL)

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United States of America Patent

PATENT NO 9576909
APP PUB NO 20160233166A1
SERIAL NO

14367711

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Abstract

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Embodiments of the present disclosure are directed towards bumpless interfaces to an embedded silicon die, in integrated circuit (IC) package assemblies. In one embodiment, a method includes forming a surrounding portion of dielectric material defining a cavity therein; placing at least one die in the cavity, the die including a contact; depositing a dielectric material on the die and the surrounding portion; etching the dielectric material to expose the contact; and depositing conductive material onto the contact. Other embodiments may be described and/or claimed.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Guzek, John S Chandler, US 89 1654
Sankman, Robert L Phoenix, US 165 1595
Teh, Weng Hong Cambridge, US 48 659

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