THREE-LEVEL SEPIC CONVERTER CIRCUIT
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United States of America Patent
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Issued Date -
Aug 11, 2016
app pub date -
Jun 25, 2015
filing date -
Feb 9, 2015
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A three-level SEPIC converter circuit includes: an input inductor connected to one side of an input terminal; first and second switches connected between the input inductor and the other side of the input terminal in series; a first capacitor and a first diode connected between the first switch and one side of an output terminal in series; a second diode and a second capacitor connected between the other side of the output terminal and the other side of the input terminal in series; first and second output capacitors connected between the output terminals; and an output inductor connected between a node between the first capacitor and the first diode and a node between the second capacitor and the second diode, wherein a node between the first switch and the second switch and a node between the first output capacitor and the second output capacitor are connected.
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