Detection of multiple accesses to a row address of a dynamic memory within a refresh period
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United States of America Patent
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Oct 23, 2018
Grant Date -
Aug 25, 2016
app pub date -
May 3, 2016
filing date -
Aug 20, 2013
priority date (Note) -
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Abstract
Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.
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