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Abstract

In a method for fabricating a field-effect transistor (FET) structure, forming a shallow trench isolation (STI) structure on a semiconductor substrate, wherein the STI structure includes dielectric structures that form one or more dielectric walled aspect ratio trapping (ART) trenches. The method further includes epitaxially growing a first semiconductor material on the semiconductor substrate and substantially filling at least one of the one or more ART trenches, and recessing the first semiconductor material down into the ART trenches selective to the dielectric structures, such that the upper surface of the first semiconductor material is below the upper surface of the dielectric structures. The method further includes epitaxially growing a second semiconductor material on top of the first semiconductor material and substantially filling the ART trenches to form a semiconductor fin that comprises an upper portion comprising the second semiconductor material and a lower portion comprising the first semiconductor material.

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First Claim