Gate-drive-on-array circuit for use with oxide semiconductor thin-film transistors
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United States of America Patent
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Oct 4, 2016
Grant Date -
Aug 25, 2016
app pub date -
Nov 5, 2014
filing date -
Oct 22, 2014
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Abstract
A gate-drive-on-array circuit for use with oxide semiconductor thin-film transistors of the present invention uses two constant-voltage negative potential sources (VSS1, VSS2) that are reduced step by step and low potentials of a high-frequency clock signal (CK(n)) and a low-frequency clock signal (LC1, LC2) to ensure an up-pull circuit portion (200) is maintained in a well closed condition during a non-operating period without being affected by the high-frequency clock signal (CK(n)) so as to ensure the circuit operates normally. Further, the first down-pull circuit portion (400) is re-designed to prevent influence thereof imposed on the outputs of the first node (Q(N)) and the output terminal (G(N)) so as to ensure the first node (Q(N)) and the output terminal (G(N)) can supply the outputs normally without generating signal distortion.
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