Methods of forming memory devices with isolation structures
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 12, 2019
Grant Date -
Sep 1, 2016
app pub date -
May 12, 2016
filing date -
Jun 12, 2007
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A first conductive region having a second conductivity type is formed in a first semiconductor over a first dielectric isolation region and having a first conductivity type. A second semiconductor having the first conductivity type is formed over the first conductive region and the first semiconductor. Isolation structures are formed extending through the second semiconductor and the first semiconductor to the first dielectric isolation region, thereby defining a first well of the second semiconductor contained within the isolation structures and a second well of the first conductive region contained within the isolation structures. A charge-storage node is formed over the first well. Source/drain regions having the second conductivity type are formed in the first well adjacent the charge-storage node. A control gate is formed over the charge-storage node. A first contact is formed to the first well. A second contact is formed to the second well through the first well.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully