CACHE SYSTEM WITH A PRIMARY CACHE AND AN OVERFLOW FIFO CACHE

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United States of America Patent

APP PUB NO 20160259728A1
SERIAL NO

14889114

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Abstract

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A cache memory system including a primary cache and an overflow cache that are searched together using a search address. The overflow cache operates as an eviction array for the primary cache. The primary cache is addressed using bits of the search address, and the overflow cache is configured as a FIFO buffer. The cache memory system may be used to implement a translation lookaside buffer for a microprocessor.

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Patent Owner(s)

Patent OwnerAddress
VIA ALLIANCE SEMICONDUCTOR CO LTDSHANGHAI 201203

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
EDDY, COLIN Austin, US 78 887
HOOKER, RODNEY E Austin, US 140 2878

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