SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

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United States of America Patent

APP PUB NO 20160260724A1
SERIAL NO

14733007

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Abstract

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According to one embodiment, a semiconductor device includes a pair of selection gate transistors arranged on a semiconductor layer, and memory cell transistors arranged on the semiconductor layer between the pair of selection gate transistors. The memory cell transistors are connected to each other in series such that every two adjacent ones of the memory cell transistors share a source/drain region. Further, the memory cell transistors are arranged in an odd number between the pair of selection gate transistors.

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Patent Owner(s)

Patent OwnerAddress
KABUSHIKI KAISHA TOSHIBA1-1 SHIBAURA 1-CHOME MINATO-KU TOKYO 105-0023

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
OHASHI, Takashi Yokkaichi, JP 80 405

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