Connections for memory electrode lines
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United States of America Patent
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Sep 11, 2018
Grant Date -
Sep 8, 2016
app pub date -
Mar 3, 2015
filing date -
Mar 3, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.
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