Importance

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Abstract

A controller can perform a first write process, in which the controller confirms a state of a buffer memory in response to a first interrupt signal, and if the buffer memory has a free space where next transmission data can be written, writes the next transmission data in the buffer memory. Further, the controller can perform a second write process, in which the controller confirms the state of the buffer memory in response to completion of the first write process, and if the buffer memory has the free space, writes the next transmission data in the buffer memory. The controller performs a new one of the first write process after having performed write of the transmission data in the second write process.

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First Claim