Three dimensional memory device including memory cells with resistance change layers
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United States of America Patent
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Nov 29, 2016
Grant Date -
Sep 15, 2016
app pub date -
Sep 9, 2015
filing date -
Mar 10, 2015
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Abstract
A memory device includes a plurality of first interconnects extending in a first direction; a plurality of second interconnects extending in the first direction; a plurality of third interconnects extending in a third direction; and memory cells each with resistance change layers provided on two side surfaces of a corresponding one of the third interconnects, which surfaces are opposite to each other in the second direction. The resistance change layers are connected to the different second interconnects. A plurality of selectors connect the third interconnects to the first interconnects. One of the selectors includes a semiconductor layer provided between the corresponding third interconnect and the corresponding first interconnect. Gates extending in the second direction and provided, via a gate insulating film, on two side surfaces that are opposite to each other in the first direction.
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