Double aspect ratio trapping
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United States of America Patent
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Oct 10, 2017
Grant Date -
Sep 15, 2016
app pub date -
May 23, 2016
filing date -
Sep 29, 2014
priority date (Note) -
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Abstract
A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant. A plurality of first semiconductor-containing pillar structures of a second semiconductor material having a second lattice constant that is greater than the first lattice constant extend upwards from a surface of the semiconductor substrate portion. A plurality of second semiconductor-containing pillar structures of a third semiconductor material having a third lattice constant that is greater than the first lattice constant extend upwards from another surface of the semiconductor substrate portion. A spacer separates each first semiconductor-containing pillar structure from each second semiconductor-containing pillar structure. Each second semiconductor-containing pillar structure has a width that is different from a width of each first semiconductor-containing pillar structure.
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