Importance

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Abstract

One embodiment includes: a substrate; a memory cell array that extends in a direction vertical to the substrate and includes a memory string having a plurality of series-coupled memory cells, and a selection transistor coupled to one end of the memory string; a wiring portion that includes a plurality of first conducting layers and a plurality of interlayer insulating films, the first conducting layers functioning as gate electrodes of the memory cell and the selection transistor, the interlayer insulating film being positioned between the first conducting layers in above and below directions; and a second conducting layer arranged on end portions of the plurality of first conducting layers of the selection transistor. The first conducting layers are electrically coupled in common to the second conducting layer.

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First Claim