High-speed latch circuits by selective use of large gate pitch
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United States of America Patent
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Nov 15, 2016
Issued Date -
N/A
app pub date -
Mar 10, 2015
filing date -
Mar 10, 2015
priority date (Note) -
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Abstract
An apparatus includes a latch circuit comprising a first set of transistors that propagate an input signal of the latch circuit to an output signal of the latch circuit and a second set of transistors that do not propagate the input signal of the latch circuit to the output signal of the latch circuit wherein a gate pitch for the first set of transistors is substantially greater than a gate pitch for the second set of transistors. Also disclosed herein, a method for improving circuit performance includes receiving an electronic representation of a plurality of latching circuits associated with a design file and increasing transistor gate pitch for selected transistors of the plurality of latching circuits, wherein the selected transistors comprise transistors that propagate an input signal of a latch to an output signal of a latch. The method also includes fabricating a chip comprising the plurality of latching circuits.
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