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Abstract

A circuit device includes a multiplexer that selects an input signal from first to n-th input signals in a time division manner and outputs the selected input signal to an output node, an A/D conversion circuit that receives the first to n-th input signals outputted from the multiplexer to the output node in a time division manner and A/D-converts the received first to n-th input signals in a time division manner, and a buffer circuit provided between an i-th input node and the output node of the multiplexer. The buffer circuit buffers the i-th input signal and outputs the buffered signal to the output node of the multiplexer in a first period. The multiplexer selects the i-th input signal and outputs the selected signal to the output node in a second period. End timing of the second period comes after end timing of the first period.

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First Claim