Multiplier pipelining optimization with a bit folding correction

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United States of America Patent

PATENT NO 9778910
SERIAL NO

14664669

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Abstract

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One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a square/multiply stage to operate on the operand, initiate a reduction stage prior to completion of the square/multiply stage, and determine whether a carry propagation has occurred.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Laurent, Pierre Quin, IE 61 1090
O'Dwyer, T J Cashel, IE 4 4

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