Cross-threaded memory system

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United States of America Patent

PATENT NO 10268619
APP PUB NO 20160275033A1
SERIAL NO

15169275

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.

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Patent Owner(s)

  • RAMBUS INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kasamsetty, Kishore Cupertino, US 12 120
Ware, Frederick A Los Altos Hills, US 758 10954

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