Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction
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United States of America Patent
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Oct 10, 2017
Issued Date -
N/A
app pub date -
Jun 1, 2016
filing date -
May 1, 2014
priority date (Note) -
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Abstract
A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.
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