Symmetrical extension junction formation with low-k spacer and dual epitaxial process in finFET device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 20, 2016
Grant Date -
Sep 29, 2016
app pub date -
Jun 24, 2015
filing date -
Mar 27, 2015
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A technique relates to a dual epitaxial process a device. A first spacer is disposed on a substrate, dummy gate, and hardmask. A first area extends in a first direction from the gate and a second area extends in an opposite direction. A doped intermediate spacer is disposed on the first spacer. A first region is opened on the substrate by removing first spacer and intermediate spacer at the first region. A first epitaxial layer is disposed in the first region. The intermediate spacer is removed from first area. A second spacer is disposed on the intermediate spacer. A second region is opened on the substrate by removing the first spacer, intermediate spacer, and second spacer. A second epitaxial layer is disposed in second region. The width of the second epitaxial layer is enlarged by annealing causing dopant in the intermediate spacer layer to flow into the second epitaxial layer.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully