FORMING TUNNELING FIELD-EFFECT TRANSISTOR WITH STACKING FAULT AND RESULTING DEVICE
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
N/A
app pub date -
Mar 25, 2015
filing date -
Mar 25, 2015
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
Devices including stacking faults in sources, or sources and drains, of TFETs are disclosed to improve tunneling efficiency. Embodiments may include a tunneling field-effect transistor comprising a substrate; a source and a drain within the substrate; a gate between the source and the drain; and a stacking fault within the source.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully