Bit-Capture Latch with Transparency Option
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United States of America Patent
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Issued Date -
Oct 6, 2016
app pub date -
Apr 2, 2015
filing date -
Apr 2, 2015
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Abstract
A novel and simple way is presented to implement a zero-capture latch circuit comprising a pair of OR AND Invert gates connected to achieve a zero-capture latch with transparency option, the output of said zero-capture latch configured to latch the input and store a zero, in functional mode, and a buffered version of the input, in test mode. A one-capture latch circuit comprising a pair of AND OR Invert gates connected to achieve a one-capture latch with transparency option, the output of said one-capture latch configured to latch the input and store a one, in functional mode, and a buffered version of the input, in test mode, is also presented. The need for a test multiplexer is eliminated, reducing the area, complexity and propagation delay of the latch circuit. The propagation delay remains constant, regardless of the mode of operation is functional or test.
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