Power-On-Reset Detector
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United States of America Patent
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Oct 18, 2016
Grant Date -
Oct 20, 2016
app pub date -
Apr 15, 2015
filing date -
Apr 15, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
Various implementations described herein are directed to an integrated circuit for power-on-reset detection. The integrated circuit may include a first stage configured to receive an input voltage signal and provide a triggering signal during ramp of the input voltage signal. The integrated circuit may include a second stage configured to receive the triggering signal from the first stage and provide an output voltage signal during ramp of the input voltage signal via gate leakage through at least one transistor.
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