PROBELESS PARALLEL TEST SYSTEM AND METHOD FOR INTEGRATED CIRCUIT
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United States of America Patent
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Issued Date -
Nov 3, 2016
app pub date -
Jul 7, 2015
filing date -
Apr 28, 2015
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Abstract
A probeless parallel test system for an integrated circuit (IC) includes an IC chip, a wireless power receiving module and a Build-In Self-Test (BIST) circuit. The wireless power receiving module is electrically connected to the IC chip. The BIST circuit is electrically connected to the wireless power receiving module and the IC chip. The wireless power receiving module, the BIST circuit and the IC chip are all formed on a wafer. The wireless power receiving module is used to provide electric power to the BIST circuit and the IC chip. When receiving the electric power, the IC chip executes a functional operation, and transmits an operation result to the BIST circuit for testing.
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