Multi-bank memory with one read port and one or more write ports per cycle
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United States of America Patent
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Aug 24, 2021
Grant Date -
Nov 3, 2016
app pub date -
Apr 7, 2016
filing date -
Apr 29, 2015
priority date (Note) -
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Abstract
A method for data storage includes, in a network element, receiving from packet-processing circuitry at least a read command and a write command, for execution in a memory array that includes multiple single-port memory banks. When the read command and the write command are to access different memory banks in the memory array, the read command and the write command are executed for the packet-processing circuitry in the different memory banks in a same memory-access cycle. When the read command and the write command are both to access a first memory bank, a second memory bank of the memory array is selected. The read command is executed in the first memory bank and the write command is executed in the second memory bank, in the same memory-access cycle.
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