Multiple read and write port memory
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United States of America Patent
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Aug 20, 2019
Grant Date -
Nov 3, 2016
app pub date -
Apr 29, 2016
filing date -
Apr 30, 2015
priority date (Note) -
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Abstract
A memory supports a write or multiple read operations in any given clock cycle. In a first clock cycle, new content data is written to a particular content memory bank among a set of content memory banks. Also in the first clock cycle, current content data is read from corresponding locations in one or more other content memory banks among the set of content memory banks. New parity data is generated based on the new content data written to the particular content memory bank and the current content data read from the one or more other content memory banks. The new parity data is written to a cache memory associated with the one or more parity banks. In a second clock cycle subsequent to the first clock cycle, the new parity data is transferred from the cache memory to one of the one or more parity memory banks.
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