MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS
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United States of America Patent
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Issued Date -
Nov 10, 2016
app pub date -
Jul 15, 2016
filing date -
May 24, 2013
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Abstract
In some embodiments, an apparatus includes processing circuitry that includes a plurality of different components configured to perform operations to generate execution results for instructions executed by the apparatus. In some embodiments the apparatus includes front-end circuitry configured to retrieve a plurality of instructions for execution and, based on identification of one or more instruction characteristics of the plurality of instructions, selectively disable one or more portions of the processing circuitry for one or more cycles during execution of the plurality of instructions. In some embodiments, this may reduce power consumption by the apparatus.
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