Method and apparatus for injecting fault and analyzing fault tolerance

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United States of America Patent

PATENT NO 10489520
APP PUB NO 20160334467A1
SERIAL NO

15154829

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Abstract

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Disclosed herein is a method and apparatus for injecting a fault and analyzing fault tolerance. The fault tolerance analysis apparatus extracts design information from a design. The fault tolerance analysis apparatus may inject a fault into a simulation of the design based on the extracted design information and parameters, and analyzes an influence of the fault on the simulation. Accordingly, in accordance with the fault tolerance analysis apparatus, fault tolerance for the fault injected into the simulation is analyzed, and the effect of the fault tolerance mechanism provided in the design is analyzed.

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Patent Owner(s)

Patent OwnerAddress
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE218 GAJEONG-RO YUSEONG-GU DAEJEON 34129

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cho, Yong-Cheol Daejeon, KR 3 11
Kwon, Young-Su Daejeon, KR 51 144

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