Methods for the submission of accelerator commands and corresponding command structures to remote hardware accelerator engines over an interconnect link
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United States of America Patent
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Jan 8, 2019
Grant Date -
Nov 17, 2016
app pub date -
Jul 28, 2016
filing date -
Mar 31, 2011
priority date (Note) -
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Abstract
An apparatus and method of submitting hardware accelerator engine commands over an interconnect link such as a PCI Express (PCIe) link. In one embodiment, the mechanism is implemented inside a PCIe Host Bridge which is integrated into a host IC or chipset. The mechanism provides an interface compatible with other integrated accelerators thereby eliminating the overhead of maintaining different programming models for local and remote accelerators. Co-processor requests issued by threads requesting a service (client threads) targeting a remote accelerator are queued and sent to a PCIe adapter and remote accelerator engine over a PCIe link. The remote accelerator engine performs the requested processing task, delivers results back to host memory and the PCIe Host Bridge performs a co-processor request completion sequence (status update, write to flag, interrupt) included in the co-processor command.
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