Simultaneously measuring degradation in multiple FETs

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United States of America Patent

PATENT NO 9702924
SERIAL NO

14716070

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Abstract

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A structure and method of testing degradation of semiconductor devices by stressing an array of several semiconductor devices at the same time and measuring the resulting degradation separately for each individual device to obtain an estimate of its expected lifetime is provided. The devices may be subjected to stress that is either in a pulsed state or in a DC state. An on-chip pulse generator may be used for stressing in the pulsed state.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Balakrishnan, Karthik White Plains, US 335 2021
Jenkins, Keith A Sleepy Hollow, US 74 454
Vezyrtzis, Christos New York, US 23 53

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