Testing integrated circuits during split fabrication
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United States of America Patent
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Aug 27, 2019
Grant Date -
Nov 24, 2016
app pub date -
Jan 21, 2015
filing date -
Jan 22, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
In one aspect, a method comprises providing at least two identical front-end-of-line (FEOL) portions of an integrated circuit (IC) in a single wafer, with at least some of each FEOL portion comprising a plurality of circuit elements; building a design back-end-of-line (BEOL) portion of the IC on at least one of the FEOL portions to form a product chip, with the design BEOL portion configuring design-type interconnections of the same plurality of circuit elements for a first instantiation; building a test-only BEOL structure on at least one of the FEOL portions to form a sacrificial test device, with the test-only BEOL structure configuring test-type interconections of the same plurality of circuit elements for a second instantiation; and testing the sacrificial test device for at least one of functionality or reliability.
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