Structure and method for BEOL nanoscale damascene sidewall-defined non-volatile memory element
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United States of America Patent
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Feb 28, 2017
Grant Date -
Nov 24, 2016
app pub date -
Jun 27, 2016
filing date -
May 20, 2015
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Abstract
An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.
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