Delay specific routings for programmable logic devices
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United States of America Patent
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Jun 27, 2017
Grant Date -
Nov 24, 2016
app pub date -
May 18, 2015
filing date -
May 18, 2015
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Abstract
Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes determining delay windows for connections in a routing of a design for a PLD, identifying invalid connections in the routing based, at least in part, on the determined delay windows, and routing the invalid connections using a dual wave maze routing process to provide a delay-specific routing for the design. The delay-specific routing may be used to generate configuration data to configure physical components of the PLD, and the configuration data may be used to program the PLD to conform to the timing constraints of the design and/or PLD.
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